1. Field of the invention
The present invention relates to the operation of a dynamic random access memory (DRAM) array. More specifically, the present invention relates to a method and structure for using a synchronous clock signal to control the internal operations of a DRAM array.
2. Description of the Prior Art
U.S. Pat. Nos. 5,708,624 and 5,615,169 issued to the same inventor and commonly owned as this Application and incorporated herein by reference in their entireties, are directed to controlling internal operations of a DRAM array. DRAM (Dynamic Random Access Memory) is well known, for instance in computer systems, for storage of data. U.S. Pat. No. 5,708,624 discloses method and structure for controlling the timing of an access to a DRAM array, for instance on an integrated circuit chip, in response to a row access signal and rising/falling edges of a clock signal. Row address decoding and the deactivation of equalization circuits are initiated when the row access signal is received and a first transition of the clock signal is detected. The row address decoding and the deactivation of the equalization circuits are completed before a second transition of the clock signal occurs.
A second transition is then used to initiate the turning on of the sense amplifiers of the DRAM array. The sense amplifiers are turned on before a third transition of the clock signal. The third transition of the clock signal is then used to initiate the column address decoding operation of the DRAM array. In an alternative embodiment, the column address decoding is initiated when a column access signal is asserted and the clock signal undergoes the third transition. The first, second and third transitions can be consecutive or non-consecutive edges of the clock signal. A problem with this prior art is that the DRAM array operations take more than one clock cycle. This is not compatible with a DRAM array that is intended for instance to be compatible with SRAM.